Si-passivated Ge nMOS gate stack with low DIT and dipole-induced superior PBTI reliability using 3D-compatible ALD caps and high-pressure anneal

Arimura, HiroakiHiroakiArimuraCott, DaireDaireCottLoo, RogerRogerLooVanherle, WendyWendyVanherleXie, QiQiXieTang, FuFuTangJiang, XiaoqiangXiaoqiangJiangFranco, JacopoJacopoFrancoSioncke, SonjaSonjaSionckeRagnarsson, Lars-AkeLars-AkeRagnarssonChiu, EddieEddieChiuLu, XiaowanXiaowanLuGeypen, JefJefGeypenBender, HugoHugoBenderMaes, JanJanMaesGivens, MichaelMichaelGivensSibaja-Hernandez, ArturoArturoSibaja-HernandezWostyn, KurtKurtWostynBoccardi, GuillaumeGuillaumeBoccardiMitard, JeromeJeromeMitardCollaert, NadineNadineCollaertMocuta, DanDanMocuta2021-10-232021-10-232016https://imec-publications.be/handle/20.500.12860/26290Si-passivated Ge nMOS gate stack with low DIT and dipole-induced superior PBTI reliability using 3D-compatible ALD caps and high-pressure annealProceedings paper