Main memory organization trade-offs with DRAM and STT-MRAM options based on gem5-NVMain simulation frameworks

Perumkunnil, ManuManuPerumkunnilOh, HyungrockHyungrockOhHartmann, MatthiasMatthiasHartmannSakhare, SushilSushilSakhareTenllado, ChristianChristianTenlladoIgnacio Gomez, JoseJoseIgnacio GomezKar, Gouri SankarGouri SankarKarFurnemont, ArnaudArnaudFurnemontCatthoor, FranckyFranckyCatthoorSenni, SophianeSophianeSenniNovo, DavidDavidNovoGamatie, AbdoulayeAbdoulayeGamatieTorres, LionelLionelTorres2021-10-262021-10-262018https://imec-publications.be/handle/20.500.12860/31512Main memory organization trade-offs with DRAM and STT-MRAM options based on gem5-NVMain simulation frameworksProceedings paperhttps://ieeexplore.ieee.org/document/8341987