A hybrid design-time/run-time scheduling flow to minimise the reconfiguration overhead of FPGAs

Resano Ezcaray, Jesús JavierJesús JavierResano EzcarayVerkest, DiederikDiederikVerkestMozos, DanielDanielMozosVernalde, SergeSergeVernaldeCatthoor, FranckyFranckyCatthoor2021-10-152021-10-152004https://imec-publications.be/handle/20.500.12860/9506A hybrid design-time/run-time scheduling flow to minimise the reconfiguration overhead of FPGAsJournal article