Brunion, MoritzMoritzBrunionSharma, ArvindArvindSharmaMirabelli, GioeleGioeleMirabelliAbdi, DawitDawitAbdiZhou, YunYunZhouKükner, HalilHalilKüknerZografos, OdysseasOdysseasZografosGarcia Redondo, FernandoFernandoGarcia RedondoBiswas, DwaipayanDwaipayanBiswasHellings, GeertGeertHellingsRyckaert, JulienJulienRyckaertMyers, JamesJamesMyers2026-05-182026-05-1820242380-9248https://imec-publications.be/handle/20.500.12860/59421The routing of the Network on Chip (NoC) in many-core systems allocates floorplan resources, which are scaling slower through technology advancements than high-density logic in conventional 2D systems. In this paper we compare fine-grained disintegration of the NoC channel routing through 3D-die stacking and signals routed on wafer backside. Physical modelling using a A10 nanosheet technology suggests that extending the backside metal stack with 2 or 3 dedicated, bidirectional routing layers provides a cost effective scaling booster, and is preferable to heterogeneous 3D implementations. We estimate up to 20 % lower cost over the 3D stacking approach and the 2D baseline at 3500 signals per channel link. We see disintegration of the high-bandwidth interconnect fabric as a crucial step, especially for increasing on-chip interconnect fabric throughput demands for quickly rising core counts in high-performance server CPUs.engProceedings paper10.1109/iedm50854.2024.10873532WOS:001692734400214