Dielectric reliability of highly scaled through silicon via for wafer level 3D-SoC applications

Li, YunlongYunlongLiVan Huylenbroeck, StefaanStefaanVan HuylenbroeckDe Vos, JoeriJoeriDe VosWu, ChenChenWuStucchi, MicheleMicheleStucchiCroes, KristofKristofCroesVan der Plas, GeertGeertVan der PlasBeyer, GeraldGeraldBeyerBeyne, EricEricBeyne2021-10-252021-10-252018https://imec-publications.be/handle/20.500.12860/31183Dielectric reliability of highly scaled through silicon via for wafer level 3D-SoC applicationsMeeting abstract