Design method and algorithms for directed self-assembly aware via layout decomposition in sub-7 nm circuits

Karageorgos, IoannisIoannisKarageorgosRyckaert, JulienJulienRyckaertGronheid, RoelRoelGronheidTung, Maryann C.Maryann C.TungWong, H.-S. PhilipH.-S. PhilipWongKarageorgos, EvangelosEvangelosKarageorgosCroes, KrisKrisCroesBekaert, JoostJoostBekaertVandenberghe, GeertGeertVandenbergheStucchi, MicheleMicheleStucchiDehaene, WimWimDehaene2021-10-232021-10-232016-111932-5150https://imec-publications.be/handle/20.500.12860/26807Design method and algorithms for directed self-assembly aware via layout decomposition in sub-7 nm circuitsJournal articlehttp://dx.doi.org/10.1117/1.JMM.15.4.043506