Challenges and opportunities of vertical FET devices using 3D circuit design layouts

Veloso, AnabelaAnabelaVelosoHuynh Bao, TrongTrongHuynh BaoRosseel, ErikErikRosseelParaschiv, VasileVasileParaschivDevriendt, KatiaKatiaDevriendtVecchio, EmmaEmmaVecchioDelvaux, ChristieChristieDelvauxChan, BTBTChanErcken, MoniqueMoniqueErckenTao, ZhengZhengTaoLi, WaikinWaikinLiAltamirano Sanchez, EfrainEfrainAltamirano SanchezVersluijs, JankoJankoVersluijsBrus, StephanStephanBrusMatagne, PhilippePhilippeMatagneWaldron, NiamhNiamhWaldronRyckaert, JulienJulienRyckaertMocuta, DanDanMocutaCollaert, NadineNadineCollaert2021-10-232021-10-232016https://imec-publications.be/handle/20.500.12860/27513Challenges and opportunities of vertical FET devices using 3D circuit design layoutsProceedings paperhttp://ieeexplore.ieee.org/document/7804409/