Moroz, VictorVictorMorozEneman, GeertGeertEnemanVerheyen, PeterPeterVerheyenNouri, FaranFaranNouriWashington, LoriLoriWashingtonSmith, LeeLeeSmithJurczak, GosiaGosiaJurczakPramanik, DipuDipuPramanik2021-10-162021-10-162005https://imec-publications.be/handle/20.500.12860/10907The impact of layout on stress-enhanced transistor performanceProceedings paper