High yield sub-0.1μm² 6T-SRAM Cells, featuring high-k/metal-gate Finfet devices, double gate patterning, a novel Fin etch strategy, full-field EUV lithography and optimized junction design & layout

Horiguchi, NaotoNaotoHoriguchiDemuynck, StevenStevenDemuynckErcken, MoniqueMoniqueErckenLocorotondo, SabrinaSabrinaLocorotondoLazzarino, FredericFredericLazzarinoAltamirano Sanchez, EfrainEfrainAltamirano SanchezHuffman, CraigCraigHuffmanBrus, StephanStephanBrusDemand, MarcMarcDemandStruyf, HerbertHerbertStruyfDe Backer, JohanJohanDe BackerHermans, JanJanHermansDelvaux, ChristieChristieDelvauxVandeweyer, TomTomVandeweyerBaerts, ChristinaChristinaBaertsMannaert, GeertGeertMannaertTruffert, VincentVincentTruffertVerluijs, jjVerluijsAlaerts, WilfriedWilfriedAlaertsDekkers, HaroldHaroldDekkersOng, PatrickPatrickOngHeylen, NancyNancyHeylenKellens, KristofKristofKellensVolders, HennyHennyVoldersHikavyy, AndriyAndriyHikavyyVrancken, ChristaChristaVranckenRakowski, MichalMichalRakowskiVerhaegen, StafStafVerhaegenVandenberghe, GeertGeertVandenbergheBeyer, GeraldGeraldBeyerLauwers, AnneAnneLauwersAbsil, PhilippePhilippeAbsilHoffmann, Thomas Y.Thomas Y.HoffmannRonse, KurtKurtRonseBiesemans, SergeSergeBiesemans2021-10-182021-10-182010https://imec-publications.be/handle/20.500.12860/17276High yield sub-0.1μm² 6T-SRAM Cells, featuring high-k/metal-gate Finfet devices, double gate patterning, a novel Fin etch strategy, full-field EUV lithography and optimized junction design & layoutProceedings paper