Joint optimization of layout and litho for SRAM and Logic towards the 20 nm node, using 193i

De Bisschop, PeterPeterDe BisschopLaenens, BartBartLaenensIwase, KazuyaKazuyaIwaseYao, TeruyoshiTeruyoshiYaoDusa, MirceaMirceaDusaSmayling, M.M.Smayling2021-10-192021-10-192011https://imec-publications.be/handle/20.500.12860/18774Joint optimization of layout and litho for SRAM and Logic towards the 20 nm node, using 193iProceedings paper