Circuit and process co-design with vertical gate-all-around nanowire FET technology to extend CMOS scaling for 5nm and beyond technologies

Huynh Bao, TrongTrongHuynh BaoYakimets, DmitryDmitryYakimetsRyckaert, JulienJulienRyckaertCiofi, IvanIvanCiofiBaert, RogierRogierBaertVeloso, AnabelaAnabelaVelosoBoemmels, JuergenJuergenBoemmelsCollaert, NadineNadineCollaertRoussel, PhilippePhilippeRousselDemuynck, StevenStevenDemuynckRaghavan, PraveenPraveenRaghavanMercha, AbdelkarimAbdelkarimMerchaTokei, ZsoltZsoltTokeiVerkest, DiederikDiederikVerkestThean, AaronAaronTheanWambacq, PietPietWambacq2021-10-222021-10-222014-09https://imec-publications.be/handle/20.500.12860/23977Circuit and process co-design with vertical gate-all-around nanowire FET technology to extend CMOS scaling for 5nm and beyond technologiesProceedings paperhttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6948768