Park, SehoonSehoonParkHemelhof, ArnoArnoHemelhofZhang, YangYangZhangGramegna, GiuseppeGiuseppeGramegnaWambacq, PietPietWambacq2026-06-042026-06-0420260018-9480https://imec-publications.be/handle/20.500.12860/59540Broadband and high-efficiency D-band frequency doubler and quadrupler chains in 250-nm indium phosphide (InP) double heterojunction bipolar transistor (DHBT) are presented, together with a design methodology that provides insights into the optimal tradeoff among conversion gain (CG), dc-RF efficiency, and the number of required buffers in the multiplier chain to achieve targeted input and output power levels. Additionally, a frequency doubler is proposed where the optimal load is defined by controlling the input common-mode impedance, allowing the load impedance to approach the matching point without sacrificing output power or efficiency. By relocating matching-related loss from the output matching network to the input common-mode path, the proposed topology enables buffer-less cascading and significantly reduces matching loss. The same technique is extended to a frequency quadrupler chain, enabling a fully buffer-less connection between cascaded impedance-adjusted frequency doublers. Thanks to the proposed doublers, the presented doubler/quadrupler exhibits a measured maximum dc-RF efficiency of 56.5%/29.7%, a peak output power of 8.9/7.4 dBm, and a peak CG of −0.1/−0.5 dB in a compact footprint of 0.24/0.37 mm2.engJournal article10.1109/tmtt.2025.3644859WOS:001663544800001