A study on power integrity in a 3D chip stack using dynamic power supply current emulation and power noise monitoring

Araga, YuukiYuukiAragaMiura, RantoRantoMiuraNagata, MakotoMakotoNagataRoda Neve, CesarCesarRoda NeveDe Vos, JoeriJoeriDe VosVan der Plas, GeertGeertVan der PlasBeyne, EricEricBeyne2021-10-222021-10-222014https://imec-publications.be/handle/20.500.12860/23496A study on power integrity in a 3D chip stack using dynamic power supply current emulation and power noise monitoringProceedings paper