Kang, ShuoShuoKangIacovo, SerenaSerenaIacovoD'have, KoenKoenD'haveOkudur, Oguzhan OrkutOguzhan OrkutOkudurAlexeev, AntonAntonAlexeevPlach, ThomasThomasPlachProbst, GernotGernotProbstDing, TaotaoTaotaoDingWimplinger, MarkusMarkusWimplingerUhrmann, ThomasThomasUhrmannDe Vos, JoeriJoeriDe VosBeyer, GeraldGeraldBeyerBeyne, EricEricBeyne2026-03-242026-03-242025979-8-3315-3933-70569-5503https://imec-publications.be/handle/20.500.12860/58933Wafer bonding is becoming a key enabling technology for advanced semiconductor devices, and as pitch scaling continues, precise wafer-to-wafer alignment becomes increasingly critical. Variations in incoming wafer shape can significantly impact bonding overlay. In this study, we investigate the bonding of wafers with saddle shape, a deformation commonly observed in 3D NAND wafers. Our findings show that bonding errors are much higher for these wafers compared to those with more symmetric shapes, with a significant portion of the overlay attributed to asymmetric scaling. Enhancing asymmetric scaling compensation is crucial for reducing bonding overlay, benefiting not only 3D NAND-to-logic bonding but also other applications involving wafers with minor shape asymmetries. A method for reducing asymmetry utilizing the top chuck control is presented, along with a discussion of its limitations. Additionally, we discuss the measurement results of backside post-thinning lithography overlay with higher order correction, which is crucial for applications requiring highly accurate backside patterning alignment.engProceedings paper10.1109/ECTC51687.2025.00347WOS:001537918100331