Evaluation of the channel engineering impact on the analog performance of deep-submicron partially depleted SOI MOSFETs at low temperatures

Hayama, K.K.HayamaOhyama, H.H.OhyamaTakakura, K.K.TakakuraRafi, J.M.J.M.RafiMercha, AbdelkarimAbdelkarimMerchaSimoen, EddyEddySimoenClaeys, CorCorClaeys2021-10-152021-10-152004https://imec-publications.be/handle/20.500.12860/9002Evaluation of the channel engineering impact on the analog performance of deep-submicron partially depleted SOI MOSFETs at low temperaturesProceedings paper