Layout Considerations of Logic Designs Using an N-layer 3D Nanofabric Process Flow

Giacomin, EdouardEdouardGiacominBoemmels, JuergenJuergenBoemmelsRyckaert, JulienJulienRyckaertCatthoor, FranckyFranckyCatthoorGaillardon, Pierre-EmmanuelPierre-EmmanuelGaillardon2022-01-182021-11-022022-01-1820202324-8432WOS:000658853800007https://imec-publications.be/handle/20.500.12860/37845Layout Considerations of Logic Designs Using an N-layer 3D Nanofabric Process FlowProceedings paper10.1109/VLSI-SOC46417.2020.9344089978-1-7281-5409-1WOS:000658853800007