Statistical timing analysis considering device and interconnect variability for BEOL requirements in the 5-nm node and beyond

Huynh Bao, TrongTrongHuynh BaoRyckaert, JulienJulienRyckaertTokei, ZsoltZsoltTokeiMercha, AbdelkarimAbdelkarimMerchaVerkest, DiederikDiederikVerkestThean, AaronAaronThean2021-10-242021-10-242017-051063-8210https://imec-publications.be/handle/20.500.12860/28555Statistical timing analysis considering device and interconnect variability for BEOL requirements in the 5-nm node and beyondJournal articlehttps://doi.org/10.1109/TVLSI.2017.2647853