Comprehensive analysis of the impact of single and arrays of through silicon vias induced stress on high-k / metal gate CMOS performances

Mercha, AbdelkarimAbdelkarimMerchaVan der Plas, GeertGeertVan der PlasMoroz, V.V.MorozDe Wolf, IngridIngridDe WolfAsimakopoulos, PanagiotisPanagiotisAsimakopoulosMinas, NikolaosNikolaosMinasDomae, ShinichiShinichiDomaePerry, DanDanPerryChoi, M.M.ChoiRedolfi, AugustoAugustoRedolfiOkoro, ChukwudiChukwudiOkoroYang, YuYuYangVan Olmen, JanJanVan OlmenThangaraju, SarasvathiSarasvathiThangarajuSabuncuoglu Tezcan, DenizDenizSabuncuoglu TezcanSoussan, PhilippePhilippeSoussanCho, Jong HoonJong HoonChoYakovlev, A.A.YakovlevMarchal, PolPolMarchalTravaly, YoussefYoussefTravalyBeyne, EricEricBeyneBiesemans, SergeSergeBiesemansSwinnen, BartBartSwinnen2021-10-182021-10-182010https://imec-publications.be/handle/20.500.12860/17621Comprehensive analysis of the impact of single and arrays of through silicon vias induced stress on high-k / metal gate CMOS performancesProceedings paper