Systematic architecture exploration based on optimistic cycle estimation for low energy embedded processors

Taniguchi, IttetsuIttetsuTaniguchiJayapala, MuraliMuraliJayapalaRaghavan, PraveenPraveenRaghavanCatthoor, FranckyFranckyCatthoorTakeuchi, YoshinoriYoshinoriTakeuchiImai, MasaharuMasaharuImai2021-10-182021-10-182009https://imec-publications.be/handle/20.500.12860/16290Systematic architecture exploration based on optimistic cycle estimation for low energy embedded processorsProceedings paper