Lariviere, StephaneStephaneLariviereBlanco, VictorVictorBlancoVandersmissen, KevinKevinVandersmissenDe Wachter, BartBartDe WachterSangghaleh, MahtabMahtabSangghalehNafus, K.K.NafusFeurprier, Y.Y.FeurprierWako, Y.Y.WakoFukui, N.N.FukuiDe Poortere, E. P.E. P.De PoortereYao, C-H.C-H.YaoHsu, A.A.HsuTabery, C.C.TaberyDoise, J.J.DoiseDe Schepper, P.P.De SchepperGuzman, N.N.Guzman2026-03-192026-03-192025979-8-3315-3782-12380-632Xhttps://imec-publications.be/handle/20.500.12860/58873This work presents the development of a single-layer damascene short loop process to evaluate the patterning performance of single-exposure 0.55 NA lithography. Electrical readouts of up to 3cm long meander and fork structures are used to assess yield across various pitch dimensions. Preliminary results demonstrate successful combo yield for pitches from 32nm to 20nm.engElectrical test demonstration for 0.55 NA EUV single patterning damascene processProceedings paper10.1109/IITC66087.2025.11075462WOS:001554227600058