DfT architecture and ATPG for interconnect tests of JEDEC wide-IO memory-on-logic die stacks

Deutsch, SergejSergejDeutschKeller, BrionBrionKellerChickermane, VivekVivekChickermaneMukherjee, SubhasishSubhasishMukherjeeSood, NavdeepNavdeepSoodGoel, Sandeep K.Sandeep K.GoelChen, Ji-JanJi-JanChenMehta, AshokAshokMehtaLee, FrankFrankLeeMarinissen, Erik JanErik JanMarinissen2021-10-202021-10-202012-11https://imec-publications.be/handle/20.500.12860/20600DfT architecture and ATPG for interconnect tests of JEDEC wide-IO memory-on-logic die stacksProceedings paper