Device challenges for logic scaling for sub-5 nm node

Jang, DoyoungDoyoungJangGarcia Bardon, MarieMarieGarcia BardonYakimets, DmitryDmitryYakimetsSchuddinck, PieterPieterSchuddinckRagnarsson, Lars-AkeLars-AkeRagnarssonSharan, NehaNehaSharanParvais, BertrandBertrandParvaisSpessot, AlessioAlessioSpessotVerkest, DiederikDiederikVerkestMocuta, AndaAndaMocuta2021-10-252021-10-252018https://imec-publications.be/handle/20.500.12860/30954Device challenges for logic scaling for sub-5 nm nodeMeeting abstract