Optimization of polysilicon encapsulated LOCOS for 0.25 micron CMOS: correlation between cavity dimensions, mechanical stress, and gate oxide integrity

Badenes, GonçalGonçalBadenesRooyackers, RitaRitaRooyackersJones, S. K.S. K.JonesBazley, D.D.BazleyBeanland, R.R.BeanlandDe Wolf, IngridIngridDe WolfDeferm, LudoLudoDeferm2021-09-302021-09-301997https://imec-publications.be/handle/20.500.12860/1709Optimization of polysilicon encapsulated LOCOS for 0.25 micron CMOS: correlation between cavity dimensions, mechanical stress, and gate oxide integrityProceedings paper