Analog Figures of Merit of Vertically Stacked Silicon Nanosheets nMOSFETs With Two Different Metal Gates for the Sub-7 nm Technology Node Operating at High Temperatures

Silva, Vanessa C. P.Vanessa C. P.SilvaPerina, Welder F.Welder F.PerinaMartino, Joao A.Joao A.MartinoSimoen, EddyEddySimoenVeloso, AnabelaAnabelaVelosoAgopian, Paula G. D.Paula G. D.Agopian2022-03-072022-03-0720210018-9383WOS:000665041900072https://imec-publications.be/handle/20.500.12860/39329Analog Figures of Merit of Vertically Stacked Silicon Nanosheets nMOSFETs With Two Different Metal Gates for the Sub-7 nm Technology Node Operating at High TemperaturesJournal article10.1109/TED.2021.3077349WOS:000665041900072LOW-FREQUENCY NOISEVOLTAGESOI