CMOS scaling beyond the 90 nm CMOS technology node: shallow junction and integration challenges

Dachs, CharlesCharlesDachsSurdeanu, RaduRaduSurdeanuPawlak, BartekBartekPawlakDoornbos, GerbenGerbenDoornbosDuffy, R.R.DuffyHeringa, AncoAncoHeringaPonomarev, YouriYouriPonomarevVenezia, VincentVincentVeneziaVan Dal, MarkMarkVan DalStolk, P.P.StolkLindsay, RichardRichardLindsayHenson, KirklenKirklenHensonDieu, B.B.DieuGeenen, LucLucGeenenHoflijk, IlseIlseHoflijkRichard, OlivierOlivierRichardClarysse, TrudoTrudoClarysseBrijs, BertBertBrijsVandervorst, WilfriedWilfriedVandervorstPagès, XavierXavierPagès2021-10-152021-10-152003https://imec-publications.be/handle/20.500.12860/7374CMOS scaling beyond the 90 nm CMOS technology node: shallow junction and integration challengesProceedings paper