Overlay scaling error reduction for hybrid Die-To-Wafer bonding

Bex, PieterPieterBexGonzalez, MarioMarioGonzalezBrems, StevenStevenBremsPhommahaxay, AlainAlainPhommahaxayD'Have, KoenKoenD'HaveDhakras, PrathameshPrathameshDhakrasCuypers, Dieter H.Dieter H.CuypersLin, YeYeLinBeyne, EricEricBeyneAbdilla, JonathanJonathanAbdillaPrince, Kawsar AhmedKawsar AhmedPrinceAuer, BenediktBenediktAuerBikaljevic, DjuroDjuroBikaljevicDeubler, ManuelManuelDeublerMoura, ThiagoThiagoMouraSchmid, StefanStefanSchmidSeroglazov, PavelPavelSeroglazov2025-04-162025-02-152025-04-162024979-8-3503-9037-72687-9700WOS:001340802800026https://imec-publications.be/handle/20.500.12860/45217Overlay scaling error reduction for hybrid Die-To-Wafer bondingProceedings paper10.1109/ESTC60143.2024.10712020979-8-3503-9036-0WOS:001340802800026