Impact of elevated source drain architecture on ESD protection devices for a 90 nm CMOS technology node

Thijs, StevenStevenThijsDe Heyn, VincentVincentDe HeynVassilev, VesselinVesselinVassilevMahadeva Iyer, NatarajanNatarajanMahadeva IyerLinten, DimitriDimitriLintenJeamsaksiri, WutthinanWutthinanJeamsaksiriDaenen, T.T.DaenenJurczak, GosiaGosiaJurczakRooyackers, RitaRitaRooyackersGroeseneken, GuidoGuidoGroeseneken2021-10-152021-10-152003-09https://imec-publications.be/handle/20.500.12860/8209Impact of elevated source drain architecture on ESD protection devices for a 90 nm CMOS technology nodeProceedings paper