CMOS Scaling by Nanosheet Device Architectures and Backside Engineering

Horiguchi, NaotoNaotoHoriguchiMertens, HansHansMertensRitzenthaler, RomainRomainRitzenthalerSubramanian, SujithSujithSubramanianWeckx, PieterPieterWeckxSchuddinck, PieterPieterSchuddinckVeloso, AnabelaAnabelaVelosoYang, ShengShengYangSerbulova, KaterynaKaterynaSerbulovaRyckaert, JulienJulienRyckaert2024-12-192024-08-162024-12-192024979-8-3503-6035-6N/AWOS:001253001400098https://imec-publications.be/handle/20.500.12860/44333CMOS Scaling by Nanosheet Device Architectures and Backside EngineeringProceedings paper10.1109/VLSITSA60681.2024.10546439979-8-3503-6034-9WOS:001253001400098