Technology/system codesign and benchmarking for lateral and vertical GAA nanowire FETs at 5-nm technology node

Pan, ChenyunChenyunPanRaghavan, PraveenPraveenRaghavanYakimets, DmitryDmitryYakimetsDebacker, PeterPeterDebackerCatthoor, FranckyFranckyCatthoorCollaert, NadineNadineCollaertTokei, ZsoltZsoltTokeiVerkest, DiederikDiederikVerkestThean, AaronAaronTheanNaeemi, AzadAzadNaeemi2021-10-222021-10-2220150018-9383https://imec-publications.be/handle/20.500.12860/25731Technology/system codesign and benchmarking for lateral and vertical GAA nanowire FETs at 5-nm technology nodeJournal articlehttp://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=7181691