Test-architecture optimization and test scheduling for TSV-based 3D stacked ICs

Noia, BrandonBrandonNoiaChakrabarty, KrishnenduKrishnenduChakrabartyGoel, Sandeep K.Sandeep K.GoelMarinissen, Erik JanErik JanMarinissenVerbree, JoukeJoukeVerbree2021-10-192021-10-192011-110278-0070https://imec-publications.be/handle/20.500.12860/19490Test-architecture optimization and test scheduling for TSV-based 3D stacked ICsJournal articlehttp://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=6046180