Addressing Key Challenges for SiGe-pFin Technologies: Fin Integrity, Low-D-IT Si-cap-free Gate Stack and Optimizing the Channel Strain

Arimura, HiroakiHiroakiArimuraCapogreco, ElenaElenaCapogrecoWostyn, KurtKurtWostynEneman, GeertGeertEnemanRagnarsson, Lars-AkeLars-AkeRagnarssonBrus, StephanStephanBrusBaudot, SylvainSylvainBaudotPeter, AntonyAntonyPeterSchram, TomTomSchramFavia, PaolaPaolaFaviaRichard, OlivierOlivierRichardBender, HugoHugoBenderMitard, JeromeJeromeMitardHoriguchi, NaotoNaotoHoriguchi2021-12-142021-11-022021-12-1420200743-1562WOS:000668063000024https://imec-publications.be/handle/20.500.12860/37746Addressing Key Challenges for SiGe-pFin Technologies: Fin Integrity, Low-D-IT Si-cap-free Gate Stack and Optimizing the Channel StrainProceedings paper978-1-7281-6460-1WOS:000668063000024