A 950 MHz Clock 47.5 MHz BW 4.7 mW 67 dB SNDR Discrete Time Delta Sigma ADC Leveraging Ring Amplification and Split-Source Comparator Based Quantizer in 28 nm CMOS

Moura Santana, LucasLucasMoura SantanaMartens, EwoutEwoutMartensLagos Benites, JorgeJorgeLagos BenitesHershberg, BenjaminBenjaminHershbergWambacq, PietPietWambacqCraninckx, JanJanCraninckx2023-06-152023-06-1520220018-9200WOS:000782828000001https://imec-publications.be/handle/20.500.12860/41735A 950 MHz Clock 47.5 MHz BW 4.7 mW 67 dB SNDR Discrete Time Delta Sigma ADC Leveraging Ring Amplification and Split-Source Comparator Based Quantizer in 28 nm CMOSJournal article10.1109/JSSC.2022.3163819WOS:000782828000001