Methodology for design optimization of SOI FinFET grounded-gate NMOS devices

Thijs, StevenStevenThijsRuss, ChristianChristianRussTremouilles, DavidDavidTremouillesGriffoni, AlessioAlessioGriffoniLinten, DimitriDimitriLintenScholz, MirkoMirkoScholzCollaert, NadineNadineCollaertRooyackers, RitaRitaRooyackersJurczak, GosiaGosiaJurczakGroeseneken, GuidoGuidoGroeseneken2021-10-182021-10-1820101530-4388https://imec-publications.be/handle/20.500.12860/18082Methodology for design optimization of SOI FinFET grounded-gate NMOS devicesJournal article