Future Design Direction for SRAM Data Array: Hierarchical Subarray With Active Interconnect

Liu, Hsiao-HsuanHsiao-HsuanLiuGilardi, CarloCarloGilardiSalahuddin, Shairfe MuhammadShairfe MuhammadSalahuddinPei, ZhenlinZhenlinPeiSchuddinck, PieterPieterSchuddinckXiang, YangYangXiangWeckx, PieterPieterWeckxHellings, GeertGeertHellingsGarcia Bardon, MarieMarieGarcia BardonRyckaert, JulienJulienRyckaertPan, ChenyunChenyunPanMitra, SubhasishSubhasishMitraCatthoor, FranckyFranckyCatthoor2025-04-242024-07-042025-04-2420241549-8328WOS:001252498300001https://imec-publications.be/handle/20.500.12860/44117Future Design Direction for SRAM Data Array: Hierarchical Subarray With Active InterconnectJournal article10.1109/TCSI.2024.3410518WOS:001252498300001