Impact of Sub-µm Wafer Thinning on Latch-Up Risk in DTCO/STCO Scaling Era

Serbulova, KaterynaKaterynaSerbulovaChen, Shih-HungShih-HungChenHellings, GeertGeertHellingsVeloso, AnabelaAnabelaVelosoJourdain, AnneAnneJourdainDe Boeck, JoJoDe BoeckGroeseneken, GuidoGuidoGroeseneken2024-09-252024-03-252024-09-2520240018-9383WOS:001178964100001https://imec-publications.be/handle/20.500.12860/43728Impact of Sub-µm Wafer Thinning on Latch-Up Risk in DTCO/STCO Scaling EraJournal article10.1109/TED.2024.3367315WOS:001178964100001