Uncertainty-aware robust optimization of test-access architectures for 3D stacked ICs

Deutsch, SergejSergejDeutschChakrabarty, KrishnenduKrishnenduChakrabartyMarinissen, Erik JanErik JanMarinissen2021-10-212021-10-212013-09https://imec-publications.be/handle/20.500.12860/22259Uncertainty-aware robust optimization of test-access architectures for 3D stacked ICsProceedings paper