Die stacking using 3D-wafer level packaging copper/polymer through-Si via technology and Cu/Sn interconnect bumping

Civale, YannYannCivaleSabuncuoglu Tezcan, DenizDenizSabuncuoglu TezcanPhilipsen, HaroldHaroldPhilipsenJaenen, PatrickPatrickJaenenAgarwal, RahulRahulAgarwalDuval, FabriceFabriceDuvalSoussan, PhilippePhilippeSoussanTravaly, YoussefYoussefTravalyBeyne, EricEricBeyne2021-10-172021-10-172009https://imec-publications.be/handle/20.500.12860/15102Die stacking using 3D-wafer level packaging copper/polymer through-Si via technology and Cu/Sn interconnect bumpingProceedings paper