On-Chip I/O ESD Protection for GaN-on-SOI Integrated Circuits

Samperi, KatiaKatiaSamperiChatterjee, UrmimalaUrmimalaChatterjeePennisi, SalvatoreSalvatorePennisi2026-06-152026-06-152025979-8-3503-5684-70271-4302https://imec-publications.be/handle/20.500.12860/59680Gallium Nitride (GaN) platforms are reshaping the efficiency, frequency, and form factor of power electronics integrated circuits. However, the absence of p-channel transistors of GaN technologies makes traditional electrostatic discharge (ESD) protection for integrated circuits (ICs) ineffective. This letter proposes a protection network for input/output pins that leverages the unique conduction properties of enhancement-mode GaN transistors in the third quadrant of their current-voltage (I-V) plane. Experimental measurements confirm the viability of the proposed solution as a library element of the process design kit.engOn-Chip I/O ESD Protection for GaN-on-SOI Integrated CircuitsProceedings paper10.1109/iscas56072.2025.11044165WOS:001537918205179POWERFAILURE