3D Stacked Devices and MOT, Innovations for Post-Nanosheet CMOS Scaling

Horiguchi, NaotoNaotoHoriguchiMertens, HansHansMertensChiarella, ThomasThomasChiarellaDemuynck, StevenStevenDemuynckVega Gonzalez, VictorVictorVega GonzalezVandooren, AnneAnneVandoorenVeloso, AnabelaAnabelaVelosoGarcia Bardon, MarieMarieGarcia BardonSisto, GiulianoGiulianoSistoGupta, AnshulAnshulGuptaTokei, ZsoltZsoltTokeiBiesemans, SergeSergeBiesemansRyckaert, JulienJulienRyckaert2026-05-042026-05-0420232380-9248https://imec-publications.be/handle/20.500.12860/592763D stacked devices without area penalty from device-device space, such as complementary FET (CFET), is promising for post-nanosheet CMOS scaling. New MOL architectures, such as backside power delivery network (BSPDN) or Vertical-Horizontal-Vertical routing style, are required to connect 3D stacked devices without wiring congestions and resistance increase. Process/material innovations are necessary to enable high aspect ratio and 3D integration in CFET integration with new MOL architectures.eng3D Stacked Devices and MOT, Innovations for Post-Nanosheet CMOS ScalingProceedings paper10.1109/iedm45741.2023.10413701WOS:001693000200041PMOSNMOS