van de Burgwal, MarcelMarcelvan de BurgwalGorbunov, MaximMaximGorbunovBerti, LaurentLaurentBertiTambara, LucasLucasTambara2026-09-022026-09-022026978-3-032-14407-2978-3-032-14404-11876-1100https://imec-publications.be/handle/20.500.12860/60190The 65nm CMOS node is used for the development of DARE65T, an aerospace grade ASIC platform that can be used to design radiation-hardened-by-design ASICs with commercial foundry technology. The platform is composed of a range of IP libraries including standard cell, IO, SRAMs, as well as mixed signal IPs including PLL, current/voltage reference and ADC. All IPs are evaluated under irradiation by means of two different test vehicles, and a functional demonstrator ASIC is presented as a proof of platform readiness for flight model ASICs.engProceedings paper10.1007/978-3-032-14405-8_15WOS:001763054700015