Utilizing Keep-Out Zone (KOZ) of Through Silicon Via (TSV) for ESD protection devices in 3D stacking integrated circuits

Chen, Shih-HungShih-HungChenThijs, StevenStevenThijsLinten, DimitriDimitriLintenGroeseneken, GuidoGuidoGroeseneken2021-10-202021-10-202012https://imec-publications.be/handle/20.500.12860/20441Utilizing Keep-Out Zone (KOZ) of Through Silicon Via (TSV) for ESD protection devices in 3D stacking integrated circuitsProceedings paper