Bilayer graphene tunneling-FET for sub-0.2 V digital CMOS logic applications

Agarwal Kumar, TarunTarunAgarwal KumarNourbakhsh, AmirhasanAmirhasanNourbakhshRaghavan, PraveenPraveenRaghavanRadu, IulianaIulianaRaduVerhelst, MarianMarianVerhelstDe Gendt, StefanStefanDe GendtHeyns, MarcMarcHeynsThean, AaronAaronThean2021-10-222021-10-2220140741-3106https://imec-publications.be/handle/20.500.12860/23472Bilayer graphene tunneling-FET for sub-0.2 V digital CMOS logic applicationsJournal articlehttp://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6936851