DfT architecture and ATPG for interconnect tests of JEDEC wide-IO DRAM memory-on-Logic 2.5D/3D-stacks

Deutsch, SergejSergejDeutschChickermane, VivekVivekChickermaneKeller, BrionBrionKellerMukherjee, SubhasishSubhasishMukherjeeSood, NavdeepNavdeepSoodMarinissen, Erik JanErik JanMarinissen2021-10-202021-10-202012-05https://imec-publications.be/handle/20.500.12860/20598DfT architecture and ATPG for interconnect tests of JEDEC wide-IO DRAM memory-on-Logic 2.5D/3D-stacksProceedings paper