Wang, XinXinWangVandierendonck, AchimAchimVandierendonckGovaerts, BrunoBrunoGovaertsPannier, TinusTinusPannierGeeroms, WarreWarreGeeromsMeysmans, CaroCaroMeysmansBauwelinck, JohanJohanBauwelinckTorfs, GuyGuyTorfs2025-04-302025-04-302025-04-3020250018-9200WOS:001470803400001https://imec-publications.be/handle/20.500.12860/45571This article presents a closed-loop type burst-mode clock and data recovery (BM-CDR) circuit with fast phase offset detection using 8/3x-fractional oversampling in the periodic preamble. The proposed phase offset detector achieves a resolution of 1/8 unit intervals (UIs) with a detection time of 4 UIs. A 2x-oversampling closed-loop bang-bang CDR is performed after the phase offset detection to provide jitter filtering. The switching between these two different oversampling ratios is realized in a single multi-phase clock generator (MPCG) by changing the duty-cycle in four differential quarter-rate clocks. Furthermore, fast duty-cycle switching (DCS) is introduced in the injection-locked ring oscillator (ILRO) design to speed up the transition from one sampling ratio to another. A prototype fabricated in 28-nm CMOS achieves a locking time of 1.6 ns at 30-Gb/s data rate, a BER of 1E-12 with a recovered clock integrated rms jitter of 398.4 fs. The jitter tolerance curve shows a corner frequency around 20 MHz with a 20-dB/dec slope in the low-frequency region. The receiver including the proposed CDR consumes 75.53 mW with 0.9-V supply and occupies an area of 0.148 mm2.Journal article10.1109/JSSC.2025.3556524WOS:001470803400001DFE RECEIVERCLOCK