Wafer level packaging technology for low-loss on-chip transmission lines and inductors

Carchon, GeertGeertCarchonSun, XiaoXiaoSunDe Raedt, WalterWalterDe RaedtBeyne, EricEricBeyne2021-10-152021-10-152003https://imec-publications.be/handle/20.500.12860/7285Wafer level packaging technology for low-loss on-chip transmission lines and inductorsProceedings paper