Method for endurance optimization of the HIMOStm flash memory cell in a 90nm CMOS technology

Yao, T.T.YaoLowe, A.A.LoweVermeulen, T.T.VermeulenBellafiore, N.N.BellafioreVan Houdt, JanJanVan HoudtWellekens, DirkDirkWellekens2021-10-162021-10-162005https://imec-publications.be/handle/20.500.12860/11591Method for endurance optimization of the HIMOStm flash memory cell in a 90nm CMOS technologyProceedings paper