Threshold voltage design incompatibility between partially-depleted SOI and bulk CMOS transistors

van Meer, HansHansvan MeerLyu, Jeong-hoJeong-hoLyuKubicek, StefanStefanKubicekGeenen, LucLucGeenenDe Meyer, KristinKristinDe Meyer2021-10-142021-10-141999https://imec-publications.be/handle/20.500.12860/3939Threshold voltage design incompatibility between partially-depleted SOI and bulk CMOS transistorsProceedings paper