Optimization of wafer-level low-impedance contact CDM testers

Simicic, MarkoMarkoSimicicWu, Wei-MinWei-MinWuJack, NathanNathanJackTamura, ShinichiShinichiTamuraShimada, YoheiYoheiShimadaSawada, MasanoriMasanoriSawadaChen, Shih-HungShih-HungChen2021-10-292021-10-292020-11https://imec-publications.be/handle/20.500.12860/35946Optimization of wafer-level low-impedance contact CDM testersProceedings paperhttps://ieeexplore.ieee.org/document/9241215