Pei, ZhenlinZhenlinPeiLiu, Hsiao-HsuanHsiao-HsuanLiuMayahinia, MahtaMahtaMayahiniaTahoori, MehdiMehdiTahooriCatthoor, FranckyFranckyCatthoorTokei, ZsoltZsoltTokeiDubey, PrashantPrashantDubeyPan, ChenyunChenyunPan2026-01-222026-01-222025-09-011063-8210https://imec-publications.be/handle/20.500.12860/58707As technology scales down, the performance–power–area (PPA) of static random access memory (SRAM) is increasingly constrained by interconnects due to the presence of large parasitic capacitance and resistance within these structures. This article presents a co-optimization and co-design framework that integrates technology, interconnect, circuit, cache memory, and workload to optimize the overall PPA of the computing cache system through various emerging interconnect technologies under software and hardware conditions. Moreover, we present the differential transmission line (DTL), which is utilized as a hybrid with conventional wires with repeater insertion. The proposed methodology enables the identification of the optimal design, thereby facilitating the reduction of interconnect energy and delay, considering synthetic/realistic workloads and comparing DTL against traditional repeater insertion methods based on metrics of PPA, including the energy–delay–area product (EDAP) and energy–delay product (EDP), for the computing cache system. A thorough design space exploration is conducted, utilizing validated experimental subarrays at the deep scale across state-of-the-art technology nodes. Moreover, the case study assesses a range of cache system parameters, emphasizing the potential of DTL interconnect technologies to enhance cache memory PPA.engJournal article10.1109/TVLSI.2025.3595818WOS:001566820900001PERFORMANCE