Low thermal budget dual-dipole gate stacks engineered for sufficient BTI reliability in novel integration schemes

Franco, JacopoJacopoFrancoWu, ZhichengZhichengWuRzepa, GerhardGerhardRzepaVandooren, AnneAnneVandoorenArimura, HiroakiHiroakiArimuraClaes, DieterDieterClaesHoriguchi, NaotoNaotoHoriguchiCollaert, NadineNadineCollaertLinten, DimitriDimitriLintenGrasser, TiborTiborGrasserKaczer, BenBenKaczer2021-10-272021-10-272019-12https://imec-publications.be/handle/20.500.12860/32978Low thermal budget dual-dipole gate stacks engineered for sufficient BTI reliability in novel integration schemesProceedings paperhttps://ieeexplore.ieee.org/document/8731237